mirror of https://github.com/shirou/gopsutil
Merge pull request #328 from jen20/solaris-cpu
cpu: Implement Solaris support for Info()pull/330/head
shirou
8 years ago
committed by
GitHub
commit
d4c8874c19
@ -0,0 +1,189 @@
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package cpu
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import (
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"errors"
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"fmt"
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"os/exec"
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"regexp"
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"sort"
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"strconv"
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"strings"
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"github.com/shirou/gopsutil/internal/common"
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)
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var ClocksPerSec = float64(128)
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func init() {
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getconf, err := exec.LookPath("/usr/bin/getconf")
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if err != nil {
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return
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}
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out, err := invoke.Command(getconf, "CLK_TCK")
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// ignore errors
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if err == nil {
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i, err := strconv.ParseFloat(strings.TrimSpace(string(out)), 64)
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if err == nil {
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ClocksPerSec = float64(i)
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}
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}
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}
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func Times(percpu bool) ([]TimesStat, error) {
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return []TimesStat{}, common.ErrNotImplementedError
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}
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func Info() ([]InfoStat, error) {
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psrInfo, err := exec.LookPath("/usr/sbin/psrinfo")
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if err != nil {
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return nil, fmt.Errorf("Cannot find psrinfo: %s", err)
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}
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psrInfoOut, err := invoke.Command(psrInfo, "-p", "-v")
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if err != nil {
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return nil, fmt.Errorf("Cannot execute psrinfo: %s", err)
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}
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isaInfo, err := exec.LookPath("/usr/bin/isainfo")
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if err != nil {
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return nil, fmt.Errorf("Cannot find isainfo: %s", err)
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}
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isaInfoOut, err := invoke.Command(isaInfo, "-b", "-v")
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if err != nil {
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return nil, fmt.Errorf("Cannot execute isainfo: %s", err)
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}
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procs, err := parseProcessorInfo(string(psrInfoOut))
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if err != nil {
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return nil, fmt.Errorf("Error parsing psrinfo output: %s", err)
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}
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flags, err := parseISAInfo(string(isaInfoOut))
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if err != nil {
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return nil, fmt.Errorf("Error parsing isainfo output: %s", err)
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}
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result := make([]InfoStat, 0, len(flags))
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for _, proc := range procs {
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procWithFlags := proc
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procWithFlags.Flags = flags
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result = append(result, procWithFlags)
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}
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return result, nil
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}
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var flagsMatch = regexp.MustCompile(`[\w\.]+`)
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func parseISAInfo(cmdOutput string) ([]string, error) {
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words := flagsMatch.FindAllString(cmdOutput, -1)
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// Sanity check the output
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if len(words) < 4 || words[1] != "bit" || words[3] != "applications" {
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return nil, errors.New("Attempted to parse invalid isainfo output")
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}
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flags := make([]string, len(words)-4)
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for i, val := range words[4:] {
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flags[i] = val
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}
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sort.Strings(flags)
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return flags, nil
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}
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var psrInfoMatch = regexp.MustCompile(`The physical processor has (?:([\d]+) virtual processor \(([\d]+)\)|([\d]+) cores and ([\d]+) virtual processors[^\n]+)\n(?:\s+ The core has.+\n)*\s+.+ \((\w+) ([\S]+) family (.+) model (.+) step (.+) clock (.+) MHz\)\n[\s]*(.*)`)
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const (
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psrNumCoresOffset = 1
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psrNumCoresHTOffset = 3
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psrNumHTOffset = 4
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psrVendorIDOffset = 5
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psrFamilyOffset = 7
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psrModelOffset = 8
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psrStepOffset = 9
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psrClockOffset = 10
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psrModelNameOffset = 11
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)
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func parseProcessorInfo(cmdOutput string) ([]InfoStat, error) {
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matches := psrInfoMatch.FindAllStringSubmatch(cmdOutput, -1)
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var infoStatCount int32
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result := make([]InfoStat, 0, len(matches))
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for physicalIndex, physicalCPU := range matches {
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var step int32
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var clock float64
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if physicalCPU[psrStepOffset] != "" {
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stepParsed, err := strconv.ParseInt(physicalCPU[psrStepOffset], 10, 32)
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if err != nil {
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return nil, fmt.Errorf("Cannot parse value %q for step as 32-bit integer: %s", physicalCPU[9], err)
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}
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step = int32(stepParsed)
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}
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if physicalCPU[psrClockOffset] != "" {
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clockParsed, err := strconv.ParseInt(physicalCPU[psrClockOffset], 10, 64)
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if err != nil {
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return nil, fmt.Errorf("Cannot parse value %q for clock as 32-bit integer: %s", physicalCPU[10], err)
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}
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clock = float64(clockParsed)
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}
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var err error
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var numCores int64
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var numHT int64
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switch {
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case physicalCPU[psrNumCoresOffset] != "":
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numCores, err = strconv.ParseInt(physicalCPU[psrNumCoresOffset], 10, 32)
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if err != nil {
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return nil, fmt.Errorf("Cannot parse value %q for core count as 32-bit integer: %s", physicalCPU[1], err)
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}
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for i := 0; i < int(numCores); i++ {
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result = append(result, InfoStat{
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CPU: infoStatCount,
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PhysicalID: strconv.Itoa(physicalIndex),
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CoreID: strconv.Itoa(i),
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Cores: 1,
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VendorID: physicalCPU[psrVendorIDOffset],
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ModelName: physicalCPU[psrModelNameOffset],
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Family: physicalCPU[psrFamilyOffset],
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Model: physicalCPU[psrModelOffset],
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Stepping: step,
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Mhz: clock,
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})
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infoStatCount++
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}
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case physicalCPU[psrNumCoresHTOffset] != "":
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numCores, err = strconv.ParseInt(physicalCPU[psrNumCoresHTOffset], 10, 32)
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if err != nil {
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return nil, fmt.Errorf("Cannot parse value %q for core count as 32-bit integer: %s", physicalCPU[3], err)
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}
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numHT, err = strconv.ParseInt(physicalCPU[psrNumHTOffset], 10, 32)
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if err != nil {
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return nil, fmt.Errorf("Cannot parse value %q for hyperthread count as 32-bit integer: %s", physicalCPU[4], err)
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}
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for i := 0; i < int(numCores); i++ {
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result = append(result, InfoStat{
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CPU: infoStatCount,
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PhysicalID: strconv.Itoa(physicalIndex),
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CoreID: strconv.Itoa(i),
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Cores: int32(numHT) / int32(numCores),
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VendorID: physicalCPU[psrVendorIDOffset],
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ModelName: physicalCPU[psrModelNameOffset],
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Family: physicalCPU[psrFamilyOffset],
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Model: physicalCPU[psrModelOffset],
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Stepping: step,
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Mhz: clock,
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})
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infoStatCount++
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}
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default:
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return nil, errors.New("Values for cores with and without hyperthreading are both set")
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}
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}
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return result, nil
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}
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@ -0,0 +1,110 @@
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package cpu
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import (
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"io/ioutil"
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"path/filepath"
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"reflect"
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"sort"
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"testing"
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)
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func TestParseISAInfo(t *testing.T) {
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cases := []struct {
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filename string
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expected []string
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}{
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{
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"1cpu_1core_isainfo.txt",
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[]string{"rdseed", "adx", "avx2", "fma", "bmi2", "bmi1", "rdrand", "f16c", "vmx",
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"avx", "xsave", "pclmulqdq", "aes", "movbe", "sse4.2", "sse4.1", "ssse3", "popcnt",
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"tscp", "cx16", "sse3", "sse2", "sse", "fxsr", "mmx", "cmov", "amd_sysc", "cx8",
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"tsc", "fpu"},
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},
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{
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"2cpu_1core_isainfo.txt",
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[]string{"rdseed", "adx", "avx2", "fma", "bmi2", "bmi1", "rdrand", "f16c", "vmx",
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"avx", "xsave", "pclmulqdq", "aes", "movbe", "sse4.2", "sse4.1", "ssse3", "popcnt",
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"tscp", "cx16", "sse3", "sse2", "sse", "fxsr", "mmx", "cmov", "amd_sysc", "cx8",
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"tsc", "fpu"},
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},
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{
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"2cpu_8core_isainfo.txt",
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[]string{"vmx", "avx", "xsave", "pclmulqdq", "aes", "sse4.2", "sse4.1", "ssse3", "popcnt",
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"tscp", "cx16", "sse3", "sse2", "sse", "fxsr", "mmx", "cmov", "amd_sysc", "cx8",
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"tsc", "fpu"},
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},
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}
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for _, tc := range cases {
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content, err := ioutil.ReadFile(filepath.Join("expected", "solaris", tc.filename))
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if err != nil {
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t.Errorf("cannot read test case: %s", err)
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}
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sort.Strings(tc.expected)
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flags, err := parseISAInfo(string(content))
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if err != nil {
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t.Fatalf("parseISAInfo: %s", err)
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}
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if !reflect.DeepEqual(tc.expected, flags) {
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t.Fatalf("Bad flags\nExpected: %v\n Actual: %v", tc.expected, flags)
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}
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}
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}
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func TestParseProcessorInfo(t *testing.T) {
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cases := []struct {
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filename string
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expected []InfoStat
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}{
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{
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"1cpu_1core_psrinfo.txt",
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[]InfoStat{
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{CPU: 0, VendorID: "GenuineIntel", Family: "6", Model: "78", Stepping: 3, PhysicalID: "0", CoreID: "0", Cores: 1, ModelName: "Intel(r) Core(tm) i7-6567U CPU @ 3.30GHz", Mhz: 3312},
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},
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},
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{
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"2cpu_1core_psrinfo.txt",
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[]InfoStat{
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{CPU: 0, VendorID: "GenuineIntel", Family: "6", Model: "78", Stepping: 3, PhysicalID: "0", CoreID: "0", Cores: 1, ModelName: "Intel(r) Core(tm) i7-6567U CPU @ 3.30GHz", Mhz: 3312},
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{CPU: 1, VendorID: "GenuineIntel", Family: "6", Model: "78", Stepping: 3, PhysicalID: "1", CoreID: "0", Cores: 1, ModelName: "Intel(r) Core(tm) i7-6567U CPU @ 3.30GHz", Mhz: 3312},
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},
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},
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{
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"2cpu_8core_psrinfo.txt",
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[]InfoStat{
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{CPU: 0, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "0", CoreID: "0", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 1, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "0", CoreID: "1", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 2, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "0", CoreID: "2", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 3, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "0", CoreID: "3", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 4, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "0", CoreID: "4", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 5, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "0", CoreID: "5", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 6, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "0", CoreID: "6", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 7, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "0", CoreID: "7", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 8, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "1", CoreID: "0", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 9, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "1", CoreID: "1", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 10, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "1", CoreID: "2", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 11, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "1", CoreID: "3", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 12, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "1", CoreID: "4", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 13, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "1", CoreID: "5", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 14, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "1", CoreID: "6", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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{CPU: 15, VendorID: "GenuineIntel", Family: "6", Model: "45", Stepping: 7, PhysicalID: "1", CoreID: "7", Cores: 2, ModelName: "Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz", Mhz: 2600},
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},
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},
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}
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for _, tc := range cases {
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content, err := ioutil.ReadFile(filepath.Join("expected", "solaris", tc.filename))
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if err != nil {
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t.Errorf("cannot read test case: %s", err)
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}
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cpus, err := parseProcessorInfo(string(content))
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if !reflect.DeepEqual(tc.expected, cpus) {
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t.Fatalf("Bad Processor Info\nExpected: %v\n Actual: %v", tc.expected, cpus)
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}
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}
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}
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@ -0,0 +1,4 @@
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64-bit amd64 applications
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rdseed adx avx2 fma bmi2 bmi1 rdrand f16c vmx avx xsave pclmulqdq
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aes movbe sse4.2 sse4.1 ssse3 popcnt tscp cx16 sse3 sse2 sse fxsr
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mmx cmov amd_sysc cx8 tsc fpu
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@ -0,0 +1,3 @@
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The physical processor has 1 virtual processor (0)
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x86 (GenuineIntel 406E3 family 6 model 78 step 3 clock 3312 MHz)
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Intel(r) Core(tm) i7-6567U CPU @ 3.30GHz
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@ -0,0 +1,4 @@
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64-bit amd64 applications
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rdseed adx avx2 fma bmi2 bmi1 rdrand f16c vmx avx xsave pclmulqdq
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aes movbe sse4.2 sse4.1 ssse3 popcnt tscp cx16 sse3 sse2 sse fxsr
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mmx cmov amd_sysc cx8 tsc fpu
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@ -0,0 +1,6 @@
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The physical processor has 1 virtual processor (0)
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x86 (GenuineIntel 406E3 family 6 model 78 step 3 clock 3312 MHz)
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Intel(r) Core(tm) i7-6567U CPU @ 3.30GHz
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The physical processor has 1 virtual processor (1)
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x86 (GenuineIntel 406E3 family 6 model 78 step 3 clock 3312 MHz)
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Intel(r) Core(tm) i7-6567U CPU @ 3.30GHz
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@ -0,0 +1,3 @@
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64-bit amd64 applications
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vmx avx xsave pclmulqdq aes sse4.2 sse4.1 ssse3 popcnt tscp cx16
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sse3 sse2 sse fxsr mmx cmov amd_sysc cx8 tsc fpu
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@ -0,0 +1,22 @@
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The physical processor has 8 cores and 16 virtual processors (0-7 16-23)
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The core has 2 virtual processors (0 16)
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The core has 2 virtual processors (1 17)
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The core has 2 virtual processors (2 18)
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The core has 2 virtual processors (3 19)
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The core has 2 virtual processors (4 20)
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The core has 2 virtual processors (5 21)
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The core has 2 virtual processors (6 22)
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The core has 2 virtual processors (7 23)
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x86 (GenuineIntel 206D7 family 6 model 45 step 7 clock 2600 MHz)
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Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz
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The physical processor has 8 cores and 16 virtual processors (8-15 24-31)
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The core has 2 virtual processors (8 24)
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The core has 2 virtual processors (9 25)
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The core has 2 virtual processors (10 26)
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The core has 2 virtual processors (11 27)
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The core has 2 virtual processors (12 28)
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The core has 2 virtual processors (13 29)
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The core has 2 virtual processors (14 30)
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The core has 2 virtual processors (15 31)
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x86 (GenuineIntel 206D7 family 6 model 45 step 7 clock 2600 MHz)
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Intel(r) Xeon(r) CPU E5-2670 0 @ 2.60GHz
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